NicholasShectman

75 Lexington Ave Somerville MA 02144

+1.617.628.3595 +1.617.543.9265 nicholas.shectman@gmail.com

A full-time design engineering or management position, in the Boston area, which will showcase my creativity, problem-solving ability, and process expertise. Method and System for Performing Frame Recovery in a Network US Patent 6,804,316 12 October 2004 Method and Apparatus for Self-healing Ring Network with Queueing of Transit Data N. Shectman, J.C.R. Bennett, W. Milliken, and J. Rokosz Large-Capacity Content Addressable Memory with Sorted Insertion US Patent 6,252,790 26 June 2001 Packet Reordering Is Not Pathological Network Behavior J. C. R. Bennett, C. Partridge, and N. Shectman IEEE/ACM Transactions on Networking, vol. 7 no. 6 December1999 Book Review: "Switching in IP Networks, B. Davie, P. Doolan, and Y. Rekhter" Computer Communication Review, vol. 29 no. 1 January1999 Referee, IEEE Network Top Secret NSA September1997 Additional clearance history available on request. Member, Technical Staff Vanu, Inc August2007 February2009 Developed new features and bug fixes for a real-time cellular base station system in C++ on Debian Linux. Guided the GSM product team from reactive firefighting to agile process, delivering improved reliability, efficient, on-time feature delivery, and considered, prioritized defect resolution. Trained staff and developed tools to reduce escalation rate from customer support to development. Managed patch releases and provided release engineering support. Drove project scheduling to avoid resource starvation. Drove estimation, selected staff, and introduced new testing, documentation, consultant relationship, and maintenance separation practices, resulting in on-time delivery of a 4-task-year project. Developed and documented a system test and release validation process, improving system reliability without sacrificing feature agility. Introduced new static analysis techniques and supervised dynamic analysis of race conditions and threading invariant violations. Coordinated bug triage, diagnosis, and resolution, resulting in a 20-fold system reliability improvement in six weeks. Promoted to a team leadership role in April 2008 and to the lead of a new team in September 2008. Hacker ITA Software January2007 August2007 Diagnosed and fixed bugs in a Java scheduling program. Analyzed emergent behavior of complex systems. Fixed bugs and participated in new feature design as part of a team implementing an airline reservation system using XML, Oracle, and Lisp. Reviewed interview candidate code submissions. Presented explanations of difficult issues to a government customer, regaining trust for the company. Proprietor Mahonkin Heavy Industries May2000 Designed, implemented, and debugged a suite of four PalmOS timing and measurement programs. Sustained development rates of 200 SLOC per day. Built an automotive distance measurement capability in hardware and software, achieving an accuracy of 7 parts per million and halving the hardware cost compared to competing products. Designed, implemented, and debugged a PalmOS microsecond timing library, becoming the world's expert in microsecond timing for Dragonball-based PalmOS devices. Designed, implemented, and debugged a PalmOS microsecond timing library. Reimplemented and expanded suite to use modern testing and development methods as adapted to best preserve extremely high velocity in an intermittent project environment. Contributed code to open source projects. Senior Software Engineer Permabit January2001 December2006 As part of a small team, wrote a content-addressed storage software product in C++ on a Debian Linux platorm, from zero lines of code through completion. Participated in the design and implementation of a secure client/server protocol, a failsafe versioning filesystem, performant NFS fileserver software, and an extensive distributed multiplatform test infrastructure. Helped drive adoption of Extreme Programming methodology, resulting in an 8-week feature-request-to-ship-date cycle and five on-time releases. Eliminated unnecessary complexity, resulting in improved maintainability, testability, and reliability. Brought outsourced subsections in house, lowering schedule risk. Achieved high availability on commodity hardware, resulting in industry-best pricing. Implemented data security and regulatory compliance filesystem features, including releasing SnapLock compatibility before SnapLock itself was released. Designed and implemented a nonlinear aggregated-file representation to enhance block reuse. Chief Technology Officer Phi Systems May2000 September2002 Designed a large inexpensive multistage content-addressable memory. Wrote and filed a patent application which was accepted without amendment. Wrote a phased development plan, with explicit go/no-go decision points. Attracted several offers of angel funding. Senior Engineer ST Microelectronics July2000 December2000 Part of a design team for a VLIW microprocessor core, implemented in mixed Verilog and VHDL. Tasks included synthesis, design verification and debug, technology retargeting for manufacturing process and hardware simulation, integration for system-on-chip and test chip implementation, tools management, testbench, and regression test design. Network Scientist BBN Technologies October1997 May2000 Participated in the design and implementation of several different high-speed, multiprotocol routers, for internal, spinoff, and contract projects. Contracts and spinoffs included Quarry Technologies, Crescent Networks, and Avici Systems. Projects included a high-speed routing engine combining custom and embedded-processor hardware; a routing security architecture; network testbeds and demonstrations; and a multicast extension of a custom routing engine. Designed, implemented, redesigned and debugged FPGA programs. Designed, implemented, and debugged routing software for embedded processor systems. Designed, implemented, and debugged routing, measurement, testbed, and concept test software. Produced system, process, tutorial, contract proposal, and patent documentation. Supervised timing documentation and analysis. Conducted job interviews. Clearance information available on request. Engineer EVI September1996 September1997 Designed and debugged circuits, FPGA programs, and hybrid multichip modules for digital radio. Designed and debugged an FSK encoder hybrid, a complex programmable logic hybrid, and a micropower digital transmitter control hybrid. Designed various revisions of and modifications to existing hybrids. Designed and debugged prototype digital circuit boards. Debugged existing designs and hybrid substrates. Supervised schematic capture and layout of prototype and support circuitry. Interviewed job candidates. Produced system and contract proposal documentation. Top Secret clearance granted September 1997. Research Scientist Research Engineer MIT AI Lab November1994 August1996 Part of the design team for a humanoid robotic platform for artificial intelligence research. Redesigned and debugged a small scalable MIMD supercomputer, using simple shared memory and commercial microprocessor modules. Specified and designed a DSP module to be used in the supercomputer and in other lab robots. Supervised assembly and debugging of supercomputer nodes. Member, Technical Staff Harvard University Physics Department September1992 February1995 Participated in the design of a 25000-MIPS supercomputer for spectrum analysis. Designed and debugged a real-time hardware data reduction system. Captured and laid out circuit boards. Simulated hardware implementations of algorithms in C. Programmer htMUD August1994 Designed and implemented a fully-distributed Web-based conferencing system in Perl/CGI in a weekend in 1994. Encapsulated and released common code in libwww-perl forerunner. Lead Programmer MTDP February1992 August1992 Designed and debugged a multiplexing serial protocol and VT102 emulator in ANSI C. Designed a serial cacheing protocol and a dynamic memory allocation scheme. Volunteer Arisia, Inc. January1991 Held various roles, including every executive position, for a four-day annual event with 250 volunteers. Convention Chair in 1996 and 2006. Currently on the board of directors of Arisia, Inc. and two other non-profit corporations. Community Organizer Arisia, Somerville Open Studios, et al. Volunteer roles for various community events. Led organizations ranging from 2 to 250 volunteers. User Assistant Harvard FAS Computer Services March1990 March1992 Helped users with software running on macs, PCs, and UNIX and VMS systems. Technician Carnegie Observatories June1989 August1989 Designed and debugged a 3-axis linear accelerometer. Intern Harvard-Smithsonian Center for Astrophysics February1989 March1989 Reduced satellite solar irradiance data, using Awk. Programmer Carnegie Observatories October1987 August1988 Designed and debugged a serial control program for a modular spectrometer, using QuickBasic. Intern Caltech Seismological Laboratory October1986 November1986 Reduced seismic data, using GW Basic. Programmer Pasadena Software 1986 Implemented a clone of the board game RISK. Implemented an antialiased fixed-width font and text display system. MIT 50K Business Plan Competition 2002 Formed a team to commercialize my Content Addressable Memory patent. Placed in the top seven of approximately 150 entrants, and attracted several offers of angel funding. New England Region SCCA 2003 Designed, implemented, and debugged a suite of hardware and software rally equipment which contributed to a career undefeated record in class. C/C++ Perl Python Java SQL Lisp variants Verilog VHDL ABEL sh/bash/csh awk PHP scripting languages Basic variants gcc/g++ gdb gprof valgrind junit cppunit Tinderbox Doxygen Perforce Subversion CVS/RCS Clearcase RT Bugzilla mySQL PilRC/PRC-tools make variants ethereal/wireshark lint variants including Verilint Synopsys Design Compiler/FPGA Compiler Cadence NC tools SignalScan Timing Designer Xilinx custom tools Synplify ORCAD ViewLogic PADS TCP/IP Abis MGCP RTP XML/XSL BEEP MIME ATM SONET/SDH MPLS PPP BGP/SBGP/MBGP OSPF/MOSPF HTTP/CGI custom protocols pthreads smart pointers futures mix-ins template remapping exception registration function call caching design for test fault insertion health monitoring FSM equivalence modeling mixed-platform development and testing multiple code segments phase-locked loops delay-locked loops Debian Linux PalmOS Cygwin Extreme Programming Scrum Harvard University September1988 August1992 BA Mathematics ACM ACM SIGCOMM Wayne Thayer (410) 290-1919 EVI, Inc. Paul Horowitz (617) 495-3265 Harvard University